FIG. 1 shows an example of a master-sliced LSI circuit with a conventional output buffer circuit. The output of an internal logic circuit section 1 includes an output CMOS circuit 10 which comprises a P-channel MOSFET (hereinafter referred to as PMOSFET) 3 and an N-channel MOSFET (hereinafter referred to as NMOSFET) 4. The source electrode of the PMOSFET 3 is connected to a first voltage source 5 of, for example, V.sub.DD1 =3.3 V, while the source electrode of the NMOSFET 4 is connected to a ground potential point GND. The gates of the transistors 3 and 4 are connected together to a node 7 which is connected to another internal logic circuit section (not shown). The drain electrodes of the transistors are connected together at a node 8. The node 8 is connected to a junction 13 of the gate electrodes of a PMOSFET 11 and an NMOSFET 12 which form a first CMOS circuit 14 of a buffer circuit 2.
The buffer circuit 2 includes, in addition to the above-stated first CMOS circuit 14, a second CMOS circuit 17 comprising a PMOSFET 15 and an NMOSFET 16. The source electrodes of the PMOSFET's 11 and 15 are connected to a second voltage source 22 of, for example, V.sub.DD2 =5.0 V, while the source electrodes of the NMOSFET's 12 and 16 are connected to a ground potential point GND. The junction 18 of the drain electrodes of the PMOSFET 11 and the NMOSFET 12 of the first CMOS circuit 14 is connected to the junction 19 of the gate electrodes of the PMOSFET 15 and the NMOSFET 16 of the second CMOS circuit 17. The junction 20 of the drain electrodes of the PMOSFET 15 and the NMOSFET 16 of the second CMOS circuit 17 is connected to an external connection terminal 21.
Now, the operation of the circuit of FIG. 1 is described. When an input signal is applied to the master-sliced LSI circuit, an arithmetic operation is provided on the input signal in the internal logic circuit section 1 so that one of the PMOSFET 3 and the NMOSFET 4 of the output CMOS circuit 10 becomes conductive. Then, as an output representing the result of the arithmetic operation of the internal logic circuit section 1, a signal at V.sub.DD1 of the first voltage source or at ground potential GND is applied from the node 8 to the first CMOS circuit 14 of the buffer circuit 2. The first CMOS circuit 14 of the buffer circuit 2 transmits the output signal from the output CMOS circuit 10 of the internal logic circuit section 1 to the second CMOS circuit 17 in the form of a signal at V.sub.DD2 of the second voltage source or at ground potential GND. Both PMOSFET 15 and NMOSFET 16 of the second CMOS circuit 17 have a high transconductance, so that the second CMOS circuit 17 can provide at the terminal 21 a signal at V.sub.DD2 or ground potential GND having sufficient power to drive an external load of the master-sliced LSI circuit.
In the above-described master-sliced LSI circuit, signal transfer can be made without troubles if the voltage level V.sub.DD1 of the first voltage source and the voltage level V.sub.DD2 of the second voltage source are substantially equal to each other or if the difference between the two voltage levels is less than the threshold voltage of the PMOSFET 11 of the first CMOS circuit 14.
Recently, however, in order to produce master-sliced LSI's of higher performance, patterns for fabricating transistors have become finer and finer, which makes it more difficult to provide transistors with a sufficient voltage withstanding characteristic against source voltages or with minimum leakage. On the other hand, in view of the system arrangement scheme, it is preferable to use a high source voltage V.sub.DD2 for systems external to the LSI circuit as in the conventional arrangement. To this end, it has been proposed to use different voltages for internal circuits of the LSI and for a circuit interfacing the LSI and the external system. However, problems are encountered in such an arrangement. For instance, in the conventional system shown in FIG. 1, when the PMOSFET 3 of the output CMOS circuit 10 of the internal logic circuit section 1 is turned on so that the potential at the node 8 becomes V.sub.DD1, the potential at the gate electrode of the PMOSFET 11 of the first CMOS circuit 14 of the buffer circuit 2 is V.sub.DD1 and the potential at the source electrode is V.sub.DD2. If the difference between V.sub.DD1 and V.sub.DD2 is larger than the threshold voltage of the PMOSFET 11, the PMOSFET 11 is not turned off, while the NMOSFET 12 is conductive. Since both of PMOSFET 11 and NMOSFET 12 become conductive, a signal of correct potential level cannot be transferred to the second CMOS circuit 17. Furthermore, a leakage current flows through the conductive PMOSFET 11 and NMOSFET 12, which causes increase in total power consumption of the LSI.
The present invention can overcome the above-discussed problems. According to the present invention, an output buffer circuit for a master-sliced LSI circuit is provided, to which a signal from an internal logic circuit section of the master-sliced LSI circuit can be transferred, and which can transfer the thus transferred signal to an external system with no error. In addition, the output buffer circuit is formed such that undersirable leakage current flows therein.